View source for Clock and Data Recovery/Buffer Memory (Elastic Buffer)/Clock domains

==Master and slaves (slaves: regenerators or end points)==
Inside a clock domain all the clocks are locked to a [[w:Master clock|master]].

They may jitter with respect to the master and with respect to each other, but they do not drift.

[[Image:Clock domains.png|center|600px]]{{center|1=<small>The domain of a master clock</small>}}

''*Definition of '''slave clock''':<ref>[http://www.itu.int/rec/T-REC-G.810-199608-I] ITU-T Recommendation G.810 : Definitions and terminology for synchronization networks (08/96) Definition 4.2.6</ref> A clock whose timing output is phase-locked to a reference timing signal received from a higher quality clock.''

<u>From the synchronization point of view</u>, a slave Clock Recovery node may be either a regenerator or an end point:
*A '''{{anchor|regenerator}}regenerator''' extracts the clock from the incoming signal in order '''both''':
** to '''regenerate''' the incoming data and
** to '''drive the transmission''' with the regenerated clock on a further link;
*An '''end point''' uses the clock extracted from the incoming signal '''only'''  to '''regenerate''' the data (and to write them in a  memory where they can be retrieved)

::<small>In general, the slave clock needs not run at the same frequency of the master.</small>

::<small>There are cases where the frequencies are different (by the ratio of two integer numbers).</small>

::<small>When the frequencies differ, the same jitter at the master and at the slave (equal if measured in time, i.e. in seconds),<br>corresponds to different values in radian, because:</small>
{{center|1=<small><math> jitter\  [rad] </math></small> = <small><math> \tfrac{2\pi\  jitter\  [sec]}{jitter\  frequency\  [sec^{-1}]}</math></small>}}
::<small>and the jitter amount at the slave is different than at the master, by the ratio:</small>
{{center|1=<math>\frac{\omega_{slave}}{\omega_{master}}</math>}}

==Free running mode==
If a slave gets disconnected from its master, a new domain is created.
[[Image:Disconnected clock domain.png|center|500px]]{{center|1=<small>A slave creates his own domain</small>}}
*''Definition of '''free running mode''''':<ref>[http://www.itu.int/rec/T-REC-G.810-199608-I] ITU-T Recommendation G.810 : Definitions and terminology for synchronization networks (08/96): Definition 4.4.1</ref> ''An operating condition of a clock, the output signal of which is strongly influenced by the oscillating element and not controlled by servo phase-locking techniques.'' ''In this mode the clock has never had a network reference input, or the clock has lost external reference and has no access to stored data, that could be acquired from a previously connected external reference.'' '' Free-run begins when the clock output no longer reflects the influence of a connected external reference, or transition from it.'' '' Free-run terminates when the clock output has achieved lock to an external reference.''

==Buffer memory==
===Between clock domains===
If two clocks exhibit a phase difference because they have followed different paths inside the same clock domain, or because they belong to different clock domains, a buffer memory can be used to compensate that difference.<br>
The figure below illustrates the second case, where, to compensate for the phase difference of two clocks of different domains, a buffer memory is used at the point of border connection.
[[Image:Buffer between clock domains.png|center|500px]]{{center|1=<small>A buffer inserted between clock domains</small>}}

*''Definition of '''[[Clock and Data Recovery/Buffer Memory (Elastic Buffer)/Cascades of Buffers and CDRs, delays and tolerance#OVERFLOW and UNDERFLOW (SLIPS)|slips]]''':<ref>[http://www.itu.int/rec/T-REC-G.810-199608-I] ITU-T Recommendation G.810 : Definitions and terminology for synchronization networks (08/96), Definition 6.1.3</ref> Slips arise as a result of the inability of an equipment buffer store (and/or other mechanisms) to accommodate differences between the phases and/or frequencies of the incoming and outgoing signals in cases where the timing of the outgoing signal is not derived from that of the incoming signal. Slips may be controlled or uncontrolled depending on the slip control strategy.''

===Within the same clock domain===
{{anchor|phase aligner}}
Sometimes two data streams that have followed different paths within a clock domain need to converge on the same path.<br>
One of the two streams will keep its own clock, the other shall be phase aligned to it (and lose its own clock).<br>
The block that operates this alignment of phase shall be called '''''Phase Aligner'''''.

[[Image:Definition_of_Phase_Aligner..pdf‎|1200x690px|center]]<br>
<small>A phaser aligner is not exactly a slave in the ITU sense of:<br />
''A clock whose timing output is phase-locked to a reference timing signal received from a higher quality clock.''<br />
The timing output of a phase aligner is exactly the clock (without any additional impairment associated with a phase lock extraction)<br />
that is supplied to the phase aligner to perform the read operation from its elastic buffer.</small>

==The three CDR functions in the clock domain==
{| class="wikitable" width=80% style="color:red; border=1; margin: 1em auto 1em auto;"  
  |+ style="color:black;" | Three main CDR functions
|-
  ! scope="col" | &nbsp;CDR function&nbsp;
  ! scope="col" | &nbsp;Recovered data&nbsp;
  ! scope="col" | &nbsp;The slave clock&nbsp;
  ! scope="col" | &nbsp;Timing&nbsp;
  ! scope="col" | &nbsp;CDR requirements&nbsp;
|-
  ! align="center" | END POINT
  | align="center" | passed into another clock domain
  | align="center" | used throughout, then discarded
  | align="center" | SLAVE
  | align="center" | Jitter tolerance
|-
  ! align="center" | REGENERATOR
  | align="center" |sent forward with the recovered clock
  | align="center" | used throughout and sent forward to extend the clock domain
  | align="center" | SLAVE
  | align="center" | 1. Jitter tolerance 2. Little noise generation 3. Filtering out incoming noise and unwanted jitter
|-
  ! align="center" | PHASE ALIGNER
  | align="center" | sent forward with a cleaner local clock
  | align="center" | used initially, then discarded
  | align="center" | emancipated to a cleaner local clock
  | align="center" | Jitter tolerance
|}
{{clear}}

==References==
<references/>

<div class="noprint">{{Clock and Data Recovery/Pagenav2|Clock and Data Recovery/Buffer Memory (Elastic Buffer)|Clock and Data Recovery/Buffer Memory (Elastic Buffer)/Cascades of Buffers and CDRs, delays and tolerance}}</div>