View source for Digital Electronics/Mathematic and Logic Operations/Digital Adder

==Digital Adder==
Digital Adder is a digital device capable of adding two digital n-bit binary numbers, where n depends on the circuit implementation. Digital adder adds two binary numbers A and B to produce a sum S and a carry C.

==Half adder==
The Half Adder is a digital device used to add two binary bit 0 and 1 The half adder outputs a sum of the two inputs and a carry value.
: 0 + 0 = Sum 0 Carry 0
: 0 + 1 = Sum 1 Carry 0
: 1 + 0 = Sum 1 Carry 0
: 1 + 1 = Sum 0 Carry 1

===Truth Table below===
:{| class="wikitable" style="text-align:center"
! <math>A</math> !! <math>B</math> !! <math>C</math> !! <math>S</math>
|-
| 0 || 0 || 0 || 0
|-
| 0 || 1 || 0 || 1
|-
| 1 || 0 || 0 || 1
|-
| 1 || 1 || 1 || 0
|}

===Construction===
               ___________
      A ------|           |
              |   Half    |----- <math>S = A \oplus B</math>
              |   Adder   |
              |           |----- <math>C = A \cdot B</math>
      B ------|___________|



Half Adder can constructed from AND gate and XOR gate as shown below
:[[File:Half Adder.svg|Half adder circuit diagram]]

==Full adder==
A '''full adder''' is a logical circuit that performs an addition operation on three one-bit binary numbers. The full adder produces a sum of the two inputs and carry value. It can be combined with other full adders (see below) or work on its own.

===Truth Table===
:{| class="wikitable" style="text-align:center"
|-
!colspan="3"| Input !!colspan="2"| Output
|-
! <math>A</math> !! <math>B</math> !! <math>C_i</math> !! <math>C_o</math> !! <math>S</math>
|-
|  0  ||  0  ||  0  ||  0  ||  0 
|-
|  0  ||  1  ||  0  ||  0  ||  1 
|-
|  1  ||  0  ||  0  ||  0  ||  1 
|-
|  1  ||  1  ||  0  ||  1  ||  0 
|-
|  0  ||  0  ||  1  ||  0  ||  1 
|-
|  0  ||  1  ||  1  ||  1  ||  0 
|-
|  1  ||  0  ||  1  ||  1  ||  0 
|-
|  1  ||  1  ||  1  ||  1  ||  1 
|}

===Construction===
:<math>S = (A \oplus B) \oplus C_{in}</math>
:<math>C_{out} = (A \cdot B) + (C_{in} \cdot (A \oplus B)) </math>
: [[Image: Full-adder logic diagram.svg|Full adder circuit diagram<br> '''Inputs: {A, B, CarryIn} → Outputs: {Sum, CarryOut}''']]
: [[Image:1-bit full-adder.svg|200px|Schematic symbol for a 1-bit full adder]]
Note that the final OR gate before the carry-out output may be replaced by an XOR gate without altering the resulting logic. This is because the only difference between OR and XOR gates occurs when both inputs are 1; for the adder shown here, this is never possible. Using only two types of gates is convenient if one desires to implement the adder directly using common IC chips.

A full adder can be constructed from two half adders by connecting ''A'' and ''B'' to the input of one half adder, connecting the sum from that to an input to the second adder, connecting ''C<sub>i</sub>'' to the other input and OR the two carry outputs.  Equivalently, ''S'' could be made the three-bit XOR of ''A'', ''B'', and ''C<sub>i</sub>'', and ''C<sub>o</sub>'' could be made the three-bit [[majority function]] of ''A'', ''B'', and ''C<sub>i</sub>''.

==Multiple-bit adders==
===Ripple carry adder===
It is possible to create a logical circuit using multiple full adders to add ''N''-bit numbers. Each full adder inputs a ''C<sub>in</sub>'', which is the ''C<sub>out</sub>'' of the previous adder. This kind of adder is a ''ripple carry adder'', since each carry bit "ripples" to the next full adder. Note that the first (and only the first) full adder may be replaced by a half adder.

The layout of  ripple carry adder is simple, which allows for fast design time; however, the ripple carry adder is relatively slow, since each full adder must wait for the carry bit to be calculated from the previous full adder.
The [[gate delay]] can easily be calculated by inspection of the full adder circuit.
Each full adder requires three levels of logic.  In a 32-bit [ripple carry] adder, there 32 full adders, so the critical path (worst case) delay is <math>32*3=96</math> gate delays.

===Carry look-ahead adders===
{{main|Carry look-ahead adder}}

To reduce the computation time, engineers devised faster ways to add two binary numbers by using [[carry lookahead adder]]s.
They work by creating two signals (''P'' and ''G'') for each bit position, based on whether a carry is propagated through from a less significant bit position (at least one input is a '1'), a carry is generated in that bit position (both inputs are '1'), or if a carry is killed in that bit position (both inputs are '0').  In most cases, ''P'' is simply the sum output of a half-adder and ''G'' is the carry output of the same adder.  After ''P'' and ''G'' are generated the carries for every bit position are created.  Some advanced carry look ahead architectures are the [[Manchester carry chain]], [[Brent-Kung adder]], and the [[Kogge-Stone adder]].
[[Image:4-bit carry lookahead adder.svg|none|framed|4-bit adder with Carry Look Ahead]]

Some other multi-bit adder architectures break the adder into blocks.  It is possible to vary the length of these blocks based on the propagation delay of the circuits to optimize computation time.  These block based adders include the [[carry bypass adder]] which will determine ''P'' and ''G'' values for each block rather than each bit, and the [[carry select adder]] which pre-generates sum and carry values for either possible carry input to the block.

Other adder designs include the [[conditional sum adder]], [[carry skip adder]], and [[carry complete adder]].

===Lookahead Carry Unit===
{{main|Lookahead Carry Unit}}

By combining multiple carry look-ahead adders even larger adders can be created.
This can be used at multiple levels to make even larger adders.
For example, the following adder is a 64-bit adder that uses four 16-bit CLAs with two levels of LCUs.

[[Image:64-bit lookahead carry unit.svg|none|framed|A 64-bit adder]]



==Reference==
# [[w:Adder_(electronics)|Digital Adder on Wikipedia]]

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