File:CPT-fetch-execute-MBR-Memory.svg
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Size of this PNG preview of this SVG file: 782 × 434 pixels. Other resolutions: 320 × 178 pixels | 640 × 355 pixels | 1,024 × 568 pixels | 1,280 × 710 pixels | 2,560 × 1,421 pixels.
Original file (SVG file, nominally 782 × 434 pixels, file size: 19 KB)
Summary
| Description |
English: Diagram of what happens when MBR<-[Memory] ; PC <- [PC] + 1 |
| Date | |
| Source | Own work |
| Author | Pluke |
| SVG development |
Licensing
I, the copyright holder of this work, hereby publish it under the following license:
 
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This file is made available under the Creative Commons CC0 1.0 Universal Public Domain Dedication. |
| The person who associated a work with this deed has dedicated the work to the public domain by waiving all of their rights to the work worldwide under copyright law, including all related and neighboring rights, to the extent allowed by law. You can copy, modify, distribute and perform the work, even for commercial purposes, all without asking permission.
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File history
Click on a date/time to view the file as it appeared at that time.
| Date/Time | Thumbnail | Dimensions | User | Comment | |
|---|---|---|---|---|---|
| current | 00:47, 2 January 2013 | | 782 × 434 (19 KB) | wikimediacommons>Pluke | fixed font |
File usage
The following 3 pages use this file:
- A-level Computing/AQA/Computer Components, The Stored Program Concept and the Internet/Machine Level Architecture/The Fetch–Execute cycle and the role of registers within it
- A-level Computing/AQA/Paper 2/Fundamentals of computer organisation and architecture/The Fetch-Execute cycle and the role of registers within it
- A-level Computing 2009/AQA/Computer Components, The Stored Program Concept and the Internet/Machine Level Architecture/The Fetch–Execute cycle and the role of registers within it
