File:SR (Clocked) Flip-flop Diagram.svg
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Size of this PNG preview of this SVG file: 300 × 145 pixels. Other resolutions: 320 × 155 pixels | 640 × 309 pixels | 1,024 × 495 pixels | 1,280 × 619 pixels | 2,560 × 1,237 pixels.
Original file (SVG file, nominally 300 × 145 pixels, file size: 22 KB)
_Flip-flop_Diagram.svg){kind=link}
Summary
| Description | Gate-level Diagram of a Clocked NAND-gate SR Flip-flop |
| Date | |
| Source | Own Drawing in Inkscape 0.43 |
| Author | Inductiveload |
| Permission (Reusing this file) |
PD |
Licensing
|
I, the copyright holder of this work, release this work into the public domain. This applies worldwide. In some countries this may not be legally possible; if so: I grant anyone the right to use this work for any purpose, without any conditions, unless such conditions are required by law. |
File history
Click on a date/time to view the file as it appeared at that time.
| Date/Time | Thumbnail | Dimensions | User | Comment | |
|---|---|---|---|---|---|
| current | 10:33, 6 May 2009 | | 300 × 145 (22 KB) | wikimediacommons>Inductiveload | Clk -> E |
File usage
The following 4 pages use this file:
_Flip-flop_Diagram.svg){kind=link}